View LF48410JC30_8984892.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

devices incorporated video imaging products 1 lf48410 1024 x 24-bit video histogrammer 08/08/2000Clds.48410-l q q q q q 40 mhz data input and compu- tation rate q q q q q 1024 x 24-bit memory array q q q q q histograms of images up to 4k x 4k with 10-bit pixel resolution q q q q q memory array flash clear q q q q q user-programmable modes: histogram, histogram accumulate, look up table, bin accumulate, delay memory, delay and subtract, single port ram q q q q q replaces harris hsp48410 q q q q q 84-pin plcc, j-lead features description lf48410 1024 x 24-bit video histogrammer devices incorporated the lf48410 is capable of generating histograms and cumulative distribu- tion functions of video images. it may also be used as a look up table, a bin accumulator, a delay memory (delay and subtract also possible), or a single port ram. the on-chip 1024 x 24-bit memory array facilitates histograms of images up to 4k x 4k pixels with a 10-bit pixel resolution. once the histogram of a video image is stored in the memory array, the cumulative distribution function can be calculated by putting the device in histogram accumulate mode. transformation functions can be performed on pixel values when the device is in look up table mode. if the cumulative distribution function is the desired transformation func- tion, the lf48410 can calculate it and have it available for look up table mode. when the device is in delay memory mode, it functions as a video row buffer. in this mode, the lf48410 can buffer video lines as long as 1029 pixels. the device can also function as an asynchronous single port ram. during asynchronous modes, the device can be configured as a 1024 x 24, 1024 x 16, or 1024 x 8-bit ram. a flash clear function is provided which sets all memory array locations and data path registers to 0. lf48410 b lock d iagram clk address generator control wr dio i/f dio 23-0 24 counter pin 9-0 10 din 23-0 24 3 ram array data in data out wr address (to all registers) rd uws start fc function decode fct 2-0 ld mux control signals ioa 9-0 10 3 adder input control
devices incorporated lf48410 1024 x 24-bit video histogrammer 2 video imaging products 08/08/2000Clds.48410-l signal definitions power v cc and gnd +5 v power supply. all pins must be connected. clock clk master clock when operating in a synchronous mode, the rising edge of clk strobes all enabled registers. clk has no effect when operating in an asynchro- nous mode. inputs pin 9-0 pixel data input pin 9-0 provides address information to the memory array in histogram, bin accumulate, and look up table modes. data is latched on the rising edge of clk. din 23-0 data input in bin accumulate mode, din 23-0 provides data to the internal summer to be added to data already in the memory array. in look up table mode, din 23-0 is used to load the memory array with the desired values. in delay memory mode, the data to be delayed is input to the memory array using din 23-0 , and in delay and subtract mode it also provides data to be subtracted from the delayed data. in all four modes, din 23-0 is latched on the rising edge of clk. ioa 9-0 asynchronous address input ioa 9-0 provides address information to the memory array in asynchronous 16 and 24 modes. fct 2-0 function input fct 2-0 is used to put the lf48410 into one of its eight modes of operation (table 1). data is latched on the rising edge of ld. to ensure proper operation of the device, start must be high while changing modes, and there must be at least one rising edge of clk between the rising edge of ld and the falling edge of start. inputs/outputs dio 23-0 data input/output in all synchronous modes, dio 23-0 is the 24-bit registered data output port. in all asynchronous modes, dio 23-0 is both the data input and data output port for the memory array. controls start device enable start is used to enable and disable the synchronous modes of operation (except for the delay memory and delay and subtract modes). the synchronous mode sections explain how start functions in each mode. start has no effect in asynchronous modes. data is latched on the rising edge of clk. start must be held high when changing from one mode to another. to ensure proper opera- tion of the device, there must be at least one rising edge of clk between the rising edge of ld and the falling edge of start. rd read/output enable in all synchronous modes, rd is used as an output enable for dio 23-0 . when rd is low, dio 23-0 is enabled for output. when rd is high, dio 23-0 is placed in a high-impedance state. in all asynchronous modes, rd is used as a read enable for the memory array (see asynchronous mode sections for details). wr write enable in all asynchronous modes, wr is used as a write enable for the memory array (see asynchronous mode sections for details). wr has no effect in the synchronous modes. uws upper word select uws is only used in asynchronous 16 mode. if uws is low and a memory write is performed, data on dio 15-0 is written to the lower 16 bits of the addressed 24-bit word. if uws is low and a memory read is per- formed, the lower 16 bits of the addressed 24-bit word will be output on dio 15-0 . if uws is high and a memory write is performed, data on dio 7-0 is written to the upper 8 bits of the addressed 24-bit word. if uws is high and a memory read is per- formed, the upper 8 bits of the addressed 24-bit word will be output on dio 7-0 . fc flash clear when fc is low, all memory array locations and data path registers are set to 0. to ensure that flash clear functions properly, fc should not be set low until start is high (synchronous modes) or wr is high (asynchronous modes). ld function load strobe data present on fct 2-0 is latched into the lf48410 on the rising edge of ld. to ensure proper operation of the device, there must be at least one rising edge of clk between the rising edge of ld and the falling edge of start. fct 2-0 mode 0 0 0 histogram 0 0 1 histogram accumulate 0 1 0 delay and subtract 0 1 1 look up table 1 0 0 bin accumulate 1 0 1 delay memory 1 1 0 asynchronous 24 1 1 1 asynchronous 16 t able 1. lf48410 m odes
devices incorporated video imaging products 3 lf48410 1024 x 24-bit video histogrammer 08/08/2000Clds.48410-l histogram mode when the lf48410 is in this mode, the chip is configured as shown in figure 1. the memory array keeps track of how many times a particular pixel value is used in a video image. the pixel value is input on pin 9-0 and is latched on the rising edge of clk. data at the address defined by pin 9-0 is read out of the memory array and incremented by one. the data is then written back to the memory array, in the same location it was read from, and is also output on dio 23-0 (if rd is low). as long as start is low, the device will be enabled for histo- gram mode. when start is high, the device will still read pixel values, but the addres-sed data will not be incremented. the unchanged data is output on dio 23-0 and is not written back to the memory array (writing is disabled). start is delayed inter- nally three clock cycles to match the latency of the address generator. histogram accumulate mode when the lf48410 is in this mode, the chip is configured as shown in figure 2. this mode is used to calculate the cumulative distribution function of a video image. before this can be done, the histogram of the image must already be in the memory array. the internal counter is used to generate address data for the memory array. data at the address defined by the counter is read out of the memory array and added to the sum of the data from all previous address locations. this new value is written back to the memory array, in the same location where the last read occurred, and is also output on dio 23-0 (if rd is low). after all memory locations with histogram data are accumulated, the memory array will contain the cumulative distribution function. after this mode is selected, the internal counter and all data path registers are reset to zero when start is set low. every rising edge of clk causes the counter to incre- ment its output by one until the counter reaches a value of 1023. at this point, the counter will hold the value of 1023 and writing to the memory array will be disabled. as long as start is low, the device will be enabled for histogram accu- mulate mode. when start is high, the counter will still increment its address values, but the addressed data will not be added to anything. the unchanged data is output on dio 23-0 and is not written back to the memory array (writing is disabled). start is delayed internally three clock cycles to match the latency of the address generator. look up table mode when the lf48410 is in this mode, the chip is configured as shown in figure 3. this mode is used to perform fixed transformation functions on pixel values. the transformation function can be loaded into the memory array in look up table write mode, asynchronous 16/24 mode, or histogram accumulate mode. in look up table write mode, data is loaded into the memory array using din 23-0 , clk, and start. the internal counter is used to generate address data for the memory array. when start goes low, the counter is reset to zero. as long as start is low, data on din 23-0 is latched on the rising edge of clk and loaded f igure 1. h istogram m ode f igure 2. h istogram a ccumulate m ode ram array data in data out address address generator control start dio i/f dio 23-0 24 rd counter clk (to all registers) wr "0" pin 9-0 clk to all registers 10 ram array data in data out wr address address generator control start "0" "1" dio i/f dio 23-0 24 rd
devices incorporated lf48410 1024 x 24-bit video histogrammer 4 video imaging products 08/08/2000Clds.48410-l into the memory array at the address defined by the counter. the value already in the memory array at that address is output on dio 23-0 (if rd is low). every rising edge of clk causes the counter to increment its output by one until the counter reaches a value of 1023. at this point, the counter will hold the value of 1023 and writing to the memory array will be disabled. din 23-0 is delayed internally three clock cycles to match the latency of the address generator. in asynchronous 16/24 mode, data is loaded into the memory array as detailed in the asynchronous mode sections. if the cumulative distribu- tion function is the desired transfor- mation function, the memory array will contain this data as soon as the histogram accumulate function has been completed. once the memory array contains the desired data, the device needs to be put in look up table read mode by setting start high. in look up table read mode, pixel values are input on pin 9-0 and are latched on the rising edge of clk. data at the address defined by pin 9-0 is read out of the memory array and output on dio 23-0 (if rd is low). if look up table write mode was used to load the memory array, it is important to wait until the third clock cycle after start goes high to input data on pin 9-0 to insure that all data is written into the memory array before any reading is done. bin accumulate mode when the lf48410 is in this mode, the chip is configured as shown in figure 4. pin 9-0 provides address data for the memory array and is latched on the rising edge of clk. data at the address defined by pin 9-0 is read out of the memory array and added to the data on din 23-0 . this new value is written back to the memory array, in the same location where the last read occured, and is also output on dio 23-0 (if rd is low). as long as start is low, the device will be enabled for bin accumulate mode. when start is high, the device will still read address values on pin 9-0 , but the addressed data will not be added to anything. the unchanged data will be output on dio 23-0 and is not written back to the memory array (writing is disabled). start and din 23-0 are delayed internally three clock cycles to match the latency of the address generator. delay memory mode when the lf48410 is in this mode, the chip is configured as shown in figure 5. this mode allows the device to function as a row buffer. the internal counter is used to generate address data for the memory array. when start goes low, the counter is reset to zero. delay length (row length) is determined by reseting the counter every nC4 clock cycles, where n is the number of delays. for f igure 3. l ook u p t able m ode f igure 4. b in a ccumulate m ode clk address generator control start dio i/f dio 23-0 24 rd counter pin 9-0 10 din 23-0 24 3 "0" ram array data in data out wr address (to all registers) note: number in register indicates number of pipeline delays. pin 9-0 clk to all registers 10 ram array data in data out address address generator control start "0" dio i/f dio 23-0 24 rd din 23-0 24 3 note: number in register indicates number of pipeline delays. wr
devices incorporated video imaging products 5 lf48410 1024 x 24-bit video histogrammer 08/08/2000Clds.48410-l example, to set the number of delays to 10, start would have to be set low every 6 cycles. the maximum delay length is 1029 and the minimum delay length is 6. data on din 23-0 is latched on the rising edge of clk and loaded into the memory array at the address defined by the counter. data is output on dio 23-0 (if rd is low). if the counter reaches the value of 1023, the counter will hold this value and writing to the memory array will be disabled. delay and subtract mode when the lf48410 is in this mode, the chip is configured as shown in figure 6. the internal counter is used to gener- ate address data for the memory array. when start goes low, the counter is reset to zero. delay length (row length) is determined by reseting the counter every nC4 clock cycles, where n is the number of delays. the maximum delay length is 1029 and the minimum delay length is 6. data on din 23-0 is latched on the rising edge of clk and loaded into the memory array at the address defined by the counter. data is output on dio 23-0 (if rd is low). before data read from the memory array is output to dio 23-0 , input data is subtracted from it according to the following formula: out c = d (cCn+1) C d (cC3) . out c is the data sent to the output port (dio 23-0 ) on clock cycle c. d (cCn+1) is the data latched into the device on clock cycle cCn+1, and d (c- 3) is the data latched into the device on clock cycle cC3. n is the number of delays. for example, to determine what will be output on dio 23-0 on clock cycle 12 when the device is set for 10 delays, set c=12 and n=10 to obtain: out 12 = d 3 C d 9 . if the counter reaches the value of 1023, the counter will hold this value and writing to the memory array will be disabled. asynchronous 16 mode when the lf48410 is in this mode, the chip is configured as shown in figure 7. this mode allows the device to function as an asynchronous single port ram. each 24-bit memory location is split into two parts, the lower 16 bits and the upper 8 bits. ioa 9-0 addresses the 24-bit memory locations, and uws addresses the lower 16 or upper 8 bits of those locations. if uws is low, the lower 16 bits of the 24-bit memory location are addressed. if uws is high, the upper 8 bits are addressed. address data on ioa 9-0 and uws is latched into the device on the falling edge of rd or wr. if rd latches the ad dress data, a memory read is performed. data at the specified address is output on dio 15-0 (if uws was latched low) or dio 7-0 (if uws was latched high). if uws was latched low/high, dio 16-23 /dio 8-23 will output zeros during a memory read. if wr latches the address data, a memory write is performed. after the falling edge of wr latches the address, data on dio 15-0 (if uws was latched low) or dio 7-0 (if uws was latched high) is written to the ram on the rising edge of wr. f igure 6. d elay a nd s ubtract m ode f igure 5. d elay m emory m ode ram array data in data out address control start dio i/f dio 23-0 24 rd clk counter (to all registers) din 23-0 24 3 note: number in register indicates number of pipeline delays. Cdin 23-0 wr ram array data in data out address control start "0" dio i/f dio 23-0 24 rd clk counter (to all registers) din 23-0 24 3 note: number in register indicates number of pipeline delays. wr
devices incorporated lf48410 1024 x 24-bit video histogrammer 6 video imaging products 08/08/2000Clds.48410-l f igure 7. a synchronous 16/24 m ode asynchronous 24 mode when the lf48410 is in this mode, the chip is configured as shown in figure 7. in this mode, the device functions the same as when in asynchronous 16 mode except that the 24-bit memory locations are not split into two parts. all 24 bits are used during a read or write operation. when reading, data is output on dio 23-0 . when writing, data is input on dio 23-0 . uws is not used in this mode. ioa 9-0 10 ram array data in data out wr address address generator control rd dio i/f dio 23-0 24 wr uws
devices incorporated video imaging products 7 lf48410 1024 x 24-bit video histogrammer 08/08/2000Clds.48410-l storage temperature ........................................................................................................... C65c to +150c operating ambient temperature ........................................................................................... C55c to +125c v cc supply voltage with respect to ground ............................................................................ C0.5 v to +7. 0v input signal with respect to ground ............................................................................... C0.5 v to v cc + 0.5 v signal applied to high impedance output ...................................................................... C0.5 v to v cc + 0.5 v output current into low outputs ................................................................................................ ............. 25 ma latchup current ................................................................................................................ ............... > 400 ma m aximum r atings above which useful life may be impaired (notes 1, 2, 3, 8) o perating c onditions to meet specified electrical and switching characteristics mode temperature range (ambient) supply voltage active operation, commercial 0c to +70c 4.75 v v cc 5.25 v active operation, military C55c to +125c 4.50 v v cc 5.50 v symbol parameter test condition min typ max unit v oh output high voltage v cc = min., i oh = C2.0 ma 2.6 v v ol output low voltage v cc = min., i ol = 4.0 ma 0.4 v v ih input high voltage 2.2 v cc v v il input low voltage (note 3) 0.0 0.8 v i ix input current ground v in v cc (note 12) 10 a i oz output leakage current ground v out v cc (note 12) 10 a i cc1 v cc current, dynamic (notes 5, 6) 310 ma i cc2 v cc current, quiescent (note 7) 500 a c in input capacitance t a = 25c, f = 1 mhz 12 pf c out output capacitance t a = 25c, f = 1 mhz 12 pf e lectrical c haracteristics over operating conditions (note 4)
devices incorporated lf48410 1024 x 24-bit video histogrammer 8 video imaging products 08/08/2000Clds.48410-l 1234567890123456 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1234567890123456 lf48410C 30 25 15 * symbol parameter min max min max min max t cyc cycle time 30 25 15 t pwl clock pulse width low 12 10 10 t pwh clock pulse width high 12 10 10 t ps pin 9-0 setup time 13 12 5 t ph pin 9-0 hold time 2 2 2 t ds din 23-0 setup time 13 12 5 t dh din 23-0 hold time 2 2 2 t ss start setup time 13 12 5 t sh start hold time 2 2 2 t cy read/write cycle time 65 55 35 t as address setup time 15 13 5 t ah address hold time 2 2 2 t wl wr pulse width low 15 12 7 t wh wr pulse width high 15 12 5 t wds dio 23-0 setup time 15 12 5 t wdh dio 23-0 hold time 2 2 2 t rl rd pulse width low 43 35 25 t rh rd pulse width high 17 15 8 t rd rd low to dio 23-0 valid 43 35 25 t oh rd high to dio 23-0 valid 0 0 0 t ll ld pulse width 12 10 7 t ls ld setup to start 30 25 15 t fs fct 2-0 setup time 10 10 5 t fh fct 2-0 hold time 2 2 2 t fl fc pulse width 35 35 15 t d output delay 19 15 11 t ena three-state output enable delay (note 11) 19 18 15 t dis three-state output disable delay (note 11) 19 18 15 c ommercial o perating r ange (0c to +70c) notes 9, 10 (ns) switching characteristics 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *d iscontinued s peed g rade
devices incorporated video imaging products 9 lf48410 1024 x 24-bit video histogrammer 08/08/2000Clds.48410-l 1234567890123456789012345678901212345678901234 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1234567890123456789012345678901212345678901234 lf48410C 39 * 30 * 25 * symbol parameter min max min max min max t cyc cycle time 39 30 25 t pwl clock pulse width low 15 12 12 t pwh clock pulse width high 15 12 12 t ps pin 9-0 setup time 16 15 12 t ph pin 9-0 hold time 2 2 2 t ds din 23-0 setup time 16 15 12 t dh din 23-0 hold time 2 2 2 t ss start setup time 16 15 12 t sh start hold time 2 2 2 t cy read/write cycle time 80 65 55 t as address setup time 20 16 13 t ah address hold time 2 2 2 t wl wr pulse width low 20 15 12 t wh wr pulse width high 20 15 10 t wds dio 23-0 setup time 20 16 12 t wdh dio 23-0 hold time 2 2 2 t rl rd pulse width low 55 43 35 t rh rd pulse width high 20 17 15 t rd rd low to dio 23-0 valid 55 43 35 t oh rd high to dio 23-0 high z 0 0 0 t ll ld pulse width 15 12 10 t ls ld setup to start 39 30 25 t fs fct 2-0 setup time 15 12 10 t fh fct 2-0 hold time 2 2 2 t fl fc pulse width 35 35 35 t d output delay 24 19 15 t ena three-state output enable delay (note 11) 24 19 18 t dis three-state output disable delay (note 11) 27 27 18 m ilitary o perating r ange (C55c to +125c) notes 9, 10 (ns) switching characteristics 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *d iscontinued s peed g rade
devices incorporated lf48410 1024 x 24-bit video histogrammer 10 video imaging products 08/08/2000Clds.48410-l s witching w aveforms :h istogram a ccumulate m ode s witching w aveforms :h istogram m ode s witching w aveforms :b in a ccumulate m ode clk pin 9-0 dio 23-0 t ph t ps t pwh t pwl t cyc 1234567 1234 567 t ss t ss t sh t sh t d t dis t ena 123* high impedance *ram contents not changed. start rd clk dio 23-0 t pwh t pwl t cyc 1234567 t ss t ss t sh t sh t d t dis t ena 123* high impedance *ram contents not changed. start rd clk pin 9-0 dio 23-0 t ph t ps t pwh t pwl t cyc 1234567 1 234 567 t ss t ss t sh t sh t d t dis t ena 123* high impedance *ram contents not changed. din 23-0 t dh t ds 1 234 567 start rd
devices incorporated video imaging products 11 lf48410 1024 x 24-bit video histogrammer 08/08/2000Clds.48410-l s witching w aveforms :l ook u p t able r ead m ode s witching w aveforms :l ook u p t able w rite m ode s witching w aveforms :d elay m emory /d elay a nd s ubtract m ode clk din 23-0 dio 23-0 t dh t ds t pwh t pwl t cyc 1234567 123 4567 t ss t d t dis t ena 123 high impedance 4 start* rd *start must be held low a minimum of t sh after the rising edge of clk that loads the last value of din 23-0 . clk pin 9-0 dio 23-0 t dh t ds t pwh t pwl t cyc 1234567 1234 5 t ss t d t dis t ena high impedance 1 rd *start must be held high a minimum of t sh after the rising edge of clk that loads the last value of pin 9-0 . start* clk din 23-0 dio 23-0 t pwh t pwl t sh t ss t d t dis t ena high impedance 1 2 3 4 5 6 7 8 9 10 11 12 13 12345678910 1112 123 13 t sh t ss t sh t ss 14 t sh t ss t sh t ss 14 4 t cyc t dh t ds start rd shown are the waveforms for a delay length of 10.
devices incorporated lf48410 1024 x 24-bit video histogrammer 12 video imaging products 08/08/2000Clds.48410-l fct 2-0 t ll t fh t fs t ls ld start* *there must be at least one rising edge of clk between the rising edge of ld and the falling edge of start. s witching w aveforms :a synchronous r ead 16/24 m ode s witching w aveforms :a synchronous w rite 16/24 m ode s witching w aveforms :f ucntion l oad s witching w aveforms :f lash c lear t fl fc ioa 9-0 dio 23-0 uws* t wh t wds t wdh t wl t as t ah *applies only to 16-bit asynchronous mode. rd wr t cy ioa 9-0 dio 23-0 uws* t rh t rd t dis t rl t as t ah *applies only to 16-bit asynchronous mode. high impedance high impedance rd wr t cy
devices incorporated video imaging products 13 lf48410 1024 x 24-bit video histogrammer 08/08/2000Clds.48410-l 1. maximum ratings indicate stress specifications only. functional oper- ation of these products at values beyond those indicated in the operating condi- tions table is not implied. exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. the products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. this device provides hard clamping of transient undershoot and overshoot. in- put levels below ground or above v cc will be clamped beginning at C0.6 v and v cc + 0.6 v. the device can withstand indefinite operation with inputs in the range of C0.5 v to +7.0 v. device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 ma. 4. actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. supply current for a given applica- tion can be accurately approximated by: where n = total number of device outputs c = capacitive load per output v = supply voltage f = clock frequency 6. tested with all outputs changing ev- ery cycle and no load, at a 20 mhz clock rate. 7. tested with all inputs within 0.1 v of v cc or ground, no load. 8. these parameters are guaranteed but not 100% tested. ncv f 4 2 notes 9. ac specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 v (except t dis test), and input levels of nominally 0 to 3.0 v. output loading may be a resistive divider which provides for specified i oh and i ol at an output voltage of v oh min and v ol max respectively. alternatively, a diode bridge with upper and lower current sources of i oh and i ol respectively, and a balancing voltage of 1.5 v may be used. parasitic capacitance is 30 pf minimum, and may be distributed. this device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. as a result, care must be exercised in the testing of this device. the following measures are recommended: a. a 0.1 f ceramic capacitor should be installed between v cc and ground leads as close to the device under test (dut) as possible. similar capacitors should be installed between device v cc and the tester common, and device ground and tester common. b. ground and v cc supply planes must be brought directly to the dut socket or contactor fingers. c. input voltages should be adjusted to compensate for inductive ground and v cc noise to maintain required dut input levels relative to the dut ground pin. 10. each parameter is shown as a min- imum or maximum value. input re- quirements are specified from the point of view of the external system driving the chip. setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. responses from the internal circuitry are specified from the point of view of the device. output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. for the t ena test, the transition is measured to the 1.5 v crossing point with datasheet loads. for the t dis test, the transition is measured to the 200mv level from the measured steady-state output voltage with 10ma loads. the balancing volt- age, v th , is set at 3.5 v for z-to-0 and 0-to-z tests, and set at 0 v for z- to-1 and 1-to-z tests. 12. these parameters are only tested at the high temperature extreme, which is the worst case for leakage current. s1 i oh i ol v th c l dut oe 0.2 v t dis t ena 0.2 v 1.5 v 1.5 v 3.5v vth 1 z 0 z z 1 z 0 1.5 v 1.5 v 0v vth v ol * v oh * v ol * v oh * measured v ol with i oh = C10ma and i ol = 10ma measured v oh with i oh = C10ma and i ol = 10ma f igure b. t hreshold l evels f igure a. o utput l oading c ircuit
devices incorporated lf48410 1024 x 24-bit video histogrammer 14 video imaging products 08/08/2000Clds.48410-l 0c to +70c c ommercial s creening ordering information 84-pin 1 2 3 4 5 6 7 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 84 83 82 81 80 79 44 43 45 46 47 49 38 37 39 40 41 42 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 top view 8 9 10 11 78 77 76 75 36 35 34 33 50 51 52 53 fc rd start ld fct 2 fct 1 fct 0 wr gnd uws ioa 9 ioa 8 ioa 7 ioa 6 ioa 5 ioa 4 ioa 3 ioa 2 ioa 1 ioa 0 v cc din 8 din 9 din 10 din 11 din 12 din 13 din 14 din 15 din 16 din 17 gnd din 18 din 19 din 20 din 21 din 22 din 23 dio 23 dio 22 dio 21 dio 20 dio 0 dio 1 dio 2 dio 3 dio 4 dio 5 dio 6 dio 7 gnd dio 8 dio 9 dio 10 dio 11 dio 12 dio 13 dio 14 dio 15 dio 16 dio 17 dio 18 dio 19 pin 0 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 v cc clk gnd pin 9 din 0 din 1 din 2 din 3 din 4 din 5 din 6 din 7 plastic j-lead chip carrier (j3) LF48410JC30 lf48410jc25 speed 30 ns 25 ns C40c to +85c c ommercial s creening
devices incorporated video imaging products 15 lf48410 1024 x 24-bit video histogrammer 08/08/2000Clds.48410-l 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 0c to +70c c ommercial s creening C55c to +125c mil-std-883 c ompliant C55c to +125c c ommercial s creening ordering information 84-pin a b c d e f g h j k l top view through package (i.e., component side pinout) 12345 6 7 8 9 10 11 pin 2 fc rd fct 2 wr uws ioa 6 ioa 3 ioa 0 dio 0 dio 2 pin 3 pin 1 fct 0 ioa 9 ioa 8 dio 1 dio 3 pin 5 pin 4 dio 4 dio 5 pin 8 pin 7 pin 6 dio 6 dio 7 gnd v cc din 1 clk dio 9 dio 8 dio 13 pin 9 din 0 gnd dio 10 dio 12 dio 11 din 2 din 3 dio 15 dio 14 pin 0 start ld fct 1 gnd ioa 5 ioa 7 ioa 4 ioa 2 ioa 1 v cc din 4 din 6 din 14 gnd din 18 dio 18 dio 16 din 5 din 7 din 9 din 12 din 15 din 21 din 20 din 23 dio 21 dio 20 dio 17 din 8 din 10 din 11 din 13 din 16 din 17 din 19 din 22 dio 23 dio 22 dio 19 speed ceramic pin grid array (g6) discontinued package

▲Up To Search▲

Price & Availability of LF48410JC30

	To Download LF48410JC30 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .